A power-on-reset (POR) cell is a circuit that outputs a logical "1" (asserted high) when the supply voltage, the input to the POR, has reached a sufficient, valid level.
When the supply is at 0 V, the POR will output a logical "0" (asserted low). The output switches to a "1" when the supply voltage reaches a predetermined voltage level, usually 2.5 V or greater for a 3 V library. A POR cell is useful because many circuits require the application of a master reset signal only after the supply voltage reaches a valid level. When the supply voltage reaches a valid level, the master reset signal starts all clocks and states storage elements of a system so that proper operation can begin.
Present POR designs have inherent disadvantages that are evident during power cycling. Power cycling involves turning the supply on and off repeatedly, for example while remaining for as little as 1 .mu.s in each state (on or off). Power cycling can occur when a power supply is first plugged in and turned on. It can also occur due to system glitches resulting from noise or mechanical system issues. Power cycling is common in data storage devices such as hard disk drives and tape drives, and also may occur with a poor board design. During power cycling events, as the supply voltage drops to 0 V, some of the subcircuits of the POR will not necessarily discharge all the way to 0 V along with the supply voltage, i.e., there is a discharge lag time existing as a latent voltage in a subcircuit of the POR. The power cycling problem becomes worse as the supply voltage drops more rapidly, in which case it could drop much faster than the rate at which portions of the POR subcircuits are able to discharge. When the supply voltage begins to ramp up again, the POR will output a logical "1" before the supply voltage has reached a valid level due to the latent voltage that was unable to completely discharge during the ramping down of the supply voltage in the previous cycle. This problem will become worse with increasing values of the latent voltage, and the latent voltage will remain at higher levels in proportion to the frequency of the power cycle. In such instances, the output of the POR will be asserted high even when the input supply voltage is at a very low value, for example 0.7 V, and at some point the output of the POR will never go to zero. Another disadvantage of present POR designs is that the low trip point, the falling threshold input voltage at which the output will trip low, is not well controlled. As the supply voltage drops, the point at which the POR output switches from a "1" to a "0" is determined by a number of factors. First, the output will trip to a "0" whenever the latent voltage drops below a switch point of a subcircuit of the POR, generally one half the value of the input supply voltage. But the low trip point is additionally dependent upon the rate at which the input supply voltage falls. The faster the input supply voltage falls, the lower the value of the input supply voltage will be before the output trips. In extreme faster cases, the output may actually go low largely because it is tracking the supply, which is collapsing at such a fast rate. Thus, there lies a need for a power on reset cell that provides improved power cycling performance and trip point control.